The present invention relates generally to integrated circuits. More particularly, it pertains to structure and methods for improved transmission line interconnections.
The metal lines over insulators and ground planes, or metal lines buried in close proximity to dielectric insulators and used for integrated circuit interconnects are in reality transmission lines or strip lines. The use of coaxial interconnection lines for interconnections through the substrate in CMOS integrated circuits can also be termed transmission lines or strip lines. Interconnection lines on interposers or printed circuit boards can also be described as transmission lines.
Most CMOS integrated circuit interconnections rely on the transmission of a voltage step or signal across transmission lines. The driver on one end of the transmission line may simply be a CMOS inverter and the receiver a simple CMOS amplifier, differential amplifier or comparator. A voltage sense amplifier serving as the CMOS receiver presents a high impedance termination or load to the interconnection line. Most commonly used coaxial lines have an impedance of only 50 ohms or 75 ohms. This fact is problematic for several identifiable reasons. In example, the high impedance termination is troublesome because the switching time response or signal delay is determined mainly by the ability of the driver to charge up the capacitance of the transmission line to neighboring transmission lines or conducting substrates as well as the load capacitance of the voltage sense amplifier. Switching times in CMOS circuits have been limited by the ability to switch the capacitive loads of long lines and buffers, and charge these capacitances over large voltage swings to yield a voltage step signal. Also, the transmission line is generally not terminated by its characteristic impedance (i.e. impedance matched) resulting in reflections and ringing. Large noise voltages may be induced on the signal transmission line due to capacitive coupling and large voltage switching on adjacent lines. The noise voltage can be a large fraction of the signal voltage. The prior art has been to for the most part not to impedance match transmission lines. Instead, in a CMOS process the transmission lines simply terminate with a voltage sense amplifier. This is due to the fact that impedance matching with low impedance resistors is difficult to achieve in CMOS technology.
In contrast, transmission lines are generally impedance matched in ECL circuits. Low impedance resistor terminations are more easily achievable in a bipolar process. The result is that ECL gates have very low input impedances (Zin) looking back into the emitters of the emitter follower inputs (Zin=1/gm). Bipolar transistors have a large transconductance gm=(q/kT) (Idc) determined by the de emitter current (Idc) so a low impedance is easily achieved, either in matching the sending or receiving end impedances. Matched transmission lines provide better noise immunity with smaller voltage swings on the lines. Unfortunately, ECL circuits consume large amounts of power and are not applicable in a CMOS process.
Some earlier research has explored current-mode sensing in SRAM circuits with d-c sensible signal currents, and which can also be applied to charge sensing in one-transistor dynamic RAMs (DRAMs). A subnanosecond sense-amplifier response time that is essentially independent of bit-line capacitance was accomplished by relocating the large bit-line capacitance to a node within the sense amplifier. Due to the small impedance at the sensing node, the signal from the memory cell can be injected into the sense amplifier with only minimal charging or discharging of the bit-line capacitance. As a result, the voltage change on the bit line during the sense portion of a cell read access was extremely low, and this eliminates the source of most voltage noise coupling problems and minimizes the power supply bounce during sensing. The subnanosecond sense-amplifier response time, however, is probably not sensitive enough for application in today""s fastest CMOS DRAM circuits.
Another problem to solve concerning integrated circuit interconnection lines is clock skew. In high frequency circuits, clock skew can be avoided by using terminated transmission lines for clock synchronization signals. Again, correctly terminating such transmissions in the CMOS technology poses complications.
One approach describes how CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits. Since these CMOS circuits only require digital signals to operate, on-chip dc power can be reduced and impedance can be adjusted by manipulating the digital control information. This technique can also be used in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers. This simple solution is unavailable, however, for implementation with combined analog/digital circuit designs.
Transmission line performance is becoming more critical on the fastest CMOS integrated circuits where the signal rise time is becoming comparable to the signal delay on long interconnection lines even on the integrated circuit die itself.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop improved performance for transmission lines fabricated according to a CMOS process.
The above mentioned problems with CMOS line interconnections as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. Current mode line interconnections are provided which accord exemplary performance.
A first embodiment of this invention provides a current mode signaling technique over low impedance transmission lines. Low impedance transmission lines such as those which exist on CMOS integrated circuits are more amenable to current signaling over longer transmission lines. These longer transmission lines may be on the CMOS integrated circuit itself, an interconnection line between integrated circuits mounted in a module as for instance a memory module, an interposer upon which these integrated circuits are mounted, or on a printed circuit board upon which the integrated circuits are mounted. An interconnection on an integrated circuit is described in which a first end of a transmission line is coupled to a driver. The transmission line has a low characteristic impedance. The transmission line is terminated at a second end with a low input impedance CMOS technology. In one embodiment, the low input impedance CMOS technology is a current sense amplifier. This minimizes reflections and ringing, cross talk and noise as well as allows for a very fast interconnection signal response.
A second embodiment of the present invention includes a novel current sense amplifier in which feedback is introduced to lower the input impedance of the current sense amplifier. In this embodiment, the novel current sense amplifier is employed together with the current signaling technique of the present invention. The novel low input impedance CMOS circuit described here provides an improved and efficiently fabricated technique for terminating low impedance transmission lines on CMOS integrated circuits. In addition, the novel low input impedance CMOS circuit offers the following advantages: (1) the signal delay depends only on the velocity of light on the line and is easily predictable and reproducible, eliminating or allowing for compensation for signal and/or clock skew, (2) there are no reflections at the receiving end of the line and this minimizes ringing, and (3) noise signals will be smaller due to weaker coupling between lines resulting in better signal to noise ratios, the noise current will only be a small fraction of the signal current.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.